Threshold voltage sensitivity reduction of SOI four gate transistor

Threshold voltage of a SOI four gate transistor is studied to determine its dependency on different device parameters. A surface potential based analytical model is used for studying threshold voltage and an Atlas/Silvaco 3-D numerical model is also developed for the validation of the analytical model. The numerical model incorporates non-ideal effects like Shockley-Read-Hall recombination, concentration dependent mobility, Auger recombination and bandgap narrowing effect. Threshold voltage sensitivity on channel length variation is reduced by controlling device width (W) and silicon layer thickness (t_si). The idea is justified by both analytical model and numerical model.