Title :
Threshold voltage sensitivity reduction of SOI four gate transistor
Author :
Islam, Md Shariful ; Debnath, Bishwajit ; Noor, Samantha Lubaba ; Hassan, Mehdi ; Haq, A. F. M. Saniul ; Khan, M. Ziaur Rahman
Author_Institution :
Electr. & Electron. Eng., Bangladesh Univ. of Eng. & Technol., Dhaka, Bangladesh
Abstract :
Threshold voltage of a SOI four gate transistor is studied to determine its dependency on different device parameters. A surface potential based analytical model is used for studying threshold voltage and an Atlas/Silvaco 3-D numerical model is also developed for the validation of the analytical model. The numerical model incorporates non-ideal effects like Shockley-Read-Hall recombination, concentration dependent mobility, Auger recombination and bandgap narrowing effect. Threshold voltage sensitivity on channel length variation is reduced by controlling device width (W) and silicon layer thickness (tsi). The idea is justified by both analytical model and numerical model.
Keywords :
MOSFET; numerical analysis; silicon-on-insulator; Atlas-Silvaco 3D numerical model; Auger recombination; SOI MOSFET; Shockley-Read-Hall recombination; bandgap narrowing effect; channel length variation; concentration dependent mobility; device parameters; device width; four gate transistor; non-ideal effects; silicon layer thickness; surface potential based analytical model; threshold voltage sensitivity reduction; Analytical models; Equations; Logic gates; Mathematical model; Numerical models; Threshold voltage; Transistors; Four gate transistor; Minimum length; Sensitivity reduction; Threshold voltage;
Conference_Titel :
Electrical & Computer Engineering (ICECE), 2012 7th International Conference on
Conference_Location :
Dhaka
Print_ISBN :
978-1-4673-1434-3
DOI :
10.1109/ICECE.2012.6471674