Circuit technique for improving propagation delay times in CMOS source-coupled logic circuits

This paper describes high-speed circuit configurations for CMOS source-coupled logic (SCL) circuits and T-type flip-flops (T-FFs). Our circuit technique uses the transient currents in the source follower for current switching to boost the circuit operating speeds. We achieved an improvement in the propagation delay time of the SCL circuit in 0.18-μm CMOS technology of about 40% by HSPICE simulations. We have also designed a T-FF with our circuit technique. The simulation shows that our CMOS T-FF operated at about 13.4 GHz. The operation frequency of our T-FF was about 16% faster than that of the conventional one due to improvement of the propagation delay times in the negative feedback loops in flip-flop.