A power optimized decimator for sigma-delta data converters

This paper presents an optimized design technique for a decimator (or decimation filter) which is part of a 2^nd-order sigma-delta modulator with an oversampling ratio (OSR) of 128. The modulator is part of an analog-to-digital converter (ADC) designed for a digital hearing aid. The decimator takes the 1-bit modulator output at 128f_s (sampling frequency) and reduces the sampling frequency to twice the highest frequency of interest (i.e., 24-bits at f_s). This task is performed in three stages: a cascaded integrator-comb (CIC) filter, downsampling with a factor of 32, followed by a bandwidth extended and then a sharp-cutoff finite impulse response (FIR) filters, each of them downsampling with a factor of 2. Polyphase filtering and circular buffer stages are also used to reduce the power consumption. The decimator was synthesized in the 140nm NXP CMOS process and occupies an area of 0.608 mm². It presents a signal-to-noise ratio (SNR) of 85 dB while consuming 188 μW with 0.9 volts power supply (simulation results).