Design of locally-clocked asynchronous finite state machines using synchronous CAD tools

Controllers based on Synchronous Finite State Machines (SFSM) are widely used in the control unit design of embedded digital systems. These systems present critical requirements, such as power consumption, robustness, speed, etc. In this context, the asynchronous paradigm shows interesting features that fit as an alternative for the design, but the lack of appropriate tools and the high difficulty of the design are already drawbacks. This paper proposes a new method to design asynchronous FSM with local clock. The existence of a local clock reduces the requirements of asynchronous logic, enabling the synthesis in any PLD, such as CPLDs and FPGAs, without the need of satisfying any type of macro-cells mapping. Furthermore, when compared to other methods found in literature, it uses of conventional logic minimization tools that greatly facilitate the designing. The proposed method starts from a popular specification known as Extended Burst Mode (XBM) and uses a logic minimization synchronous tool for the synthesis. The achieved results show a high potential of practical implementation of this method for AFSM synthesis in PLDs.