Design of a massively parallel computing architecture for dense matrix multiplication

Transistor density made possible the design of massively parallel architectures with hundreds of cores on a single chip. Designing architectures with such high number of cores with efficient performance/area or power ratios is very challenging. In this paper we take a different approach to design many-core architectures. We start with a formal analysis of the algorithms considering architectural aspects, and then decide the structure of the architecture. To exemplify the approach we did a theoretical analysis of a dense matrix multiplication algorithm, implemented the architecture based on the theoretical model and simulated the system in SystemC. Results indicate that the proposed architecture is near two orders of magnitude more performance/area efficient than a cutting-edge general-purpose processor achieving near 1 TFLOP in a 100 mm² chip with 65 nm technology.