Design of synchronous pipeline digital systems operating in double-edge of the clock

In contemporaneous digital systems the fetch by performance is critical, many times is accomplished through of the use of the pipeline control. In these systems the activity of the clock signal is a major energy consumer. It is responsible for 15% to 45% of the total consumed energy. Once reducing the activity of the clock signal, it is possible not only a reduction of the considered energy, but also a reduction of clock skew problems and electromagnetic iteration. An interesting strategy to achieve this goal is to design the synchronous digital system to operate in transitions of both edges of the clock signal (double-edge triggered - DET), once it allows a 50% reduction in the frequency of the clock signal, although showing the same processing rate data. In this paper it is proposed a method that synthesizes synchronous digital systems with pipeline control that operate on both edges of the clock signal, using only flip-flops sensitive to a single edge of the clock signal (single-edge triggered flip-flops-SET-FF) as components of the state memory. The proposed method presents very good potential to reduce the problems associated with the clock, has a high probability of practical implementation with low penalty on area.