Managing signal and power integrity using power transmission lines and alternative signaling schemes

Signal and power integrity are crucial for ensuring good performance in high speed digital systems. As the operating frequency of digital systems increases, the power and ground bounce created by simultaneous switching noise (SSN) becomes a limiting factor for the performance of these devices. SSN is caused by parasitic inductance that exists in the power delivery network (PDN), and voltage fluctuations on the power and ground rails can lead to reduced noise margins and can limit the maximum frequency of a digital device. A new PDN design has been suggested that achieves significantly reduced SSN [1] by replacing the power plane structure with a power transmission line (PTL). Previous works have demonstrated the validity of the Power Transmission Line concept in terms of SSN reduction and power consumption reduction [1-4]. However, these works focused on small systems with just a few bits. This paper shows the effectiveness of the PTL concept on a large scale system with a large number of I/O pins through an FPGA implementation to simulate the memory interface such as DDR3.