Signal integrity design of TSV and interposer in 3D-IC

Author

Jonghyun Cho ; Joungho Kim

Author_Institution

Dept. of Electr. Eng., KAIST, Daejeon, South Korea

fYear

2013

fDate

Feb. 27 2013-March 1 2013

Firstpage

1

Lastpage

4

Abstract

Electrical characterization of through-silicon via (TSV) and interposer line becomes more important as 3-dimensional integrated circuit (3D-IC) is emerging. In this paper, TSV modeling is proposed and verified using 3D-EM simulation. The model has good correlation with the simulation both at insertion loss and TSV-to-TSV noise transfer function. Using the TSV model, signal integrity (SI) analysis is performed. Also, interposer line characteristics are analyzed both at frequency-and time- domain. As a result, SI can be considered based on the TSV and interposer line analyses for 3D IC design.

Keywords

frequency-domain analysis; integrated circuit design; integrated circuit modelling; three-dimensional integrated circuits; time-domain analysis; transfer functions; 3-dimensional integrated circuit; 3D-EM simulation; 3D-IC design; SI analysis; TSV electrical characterization; TSV modeling; TSV-to-TSV noise transfer function; frequency-domain; insertion loss; interposer line characteristics; signal integrity analysis; signal integrity design; through-silicon via; time-domain; Capacitance; Couplings; Integrated circuit modeling; Noise; Routing; Silicon; Through-silicon vias; interposer; modeling; noise coupling; thorugh-silicon via (TSV);

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (LASCAS), 2013 IEEE Fourth Latin American Symposium on

Conference_Location

Cusco

Print_ISBN

978-1-4673-4897-3

Type

conf

DOI

10.1109/LASCAS.2013.6519092

Filename

6519092