• DocumentCode
    601530
  • Title

    Dynamic gate resistance control for current balancing in parallel connected IGBTs

  • Author

    Sasaki, Masahiro ; Nishio, Haruhiko ; Ng, Wai Tung

  • Author_Institution
    Power Semiconductors Development Division, Fuji Electric Co., Ltd., Matsumoto Japan
  • fYear
    2013
  • fDate
    17-21 March 2013
  • Firstpage
    244
  • Lastpage
    249
  • Abstract
    In high power applications, switching devices such as MOSFETs and IGBTs must often be connected in parallel in order to provide higher current capability. However, the current imbalance of parallel connected IGBTs due to stray inductance, variations in device characteristics and asymmetric PCB layout, necessitates de-rating of the IGBTs. This deliberate de-rating is required in order to ensure the IGBTs function within their Safe-Operating-Area. Unfortunately, de-rating also leads to an increase in cost, size and complexity of the overall power electronics system. A current balancing method for parallel connected IGBTs using a dynamically adjustable gate driving resistance (Rg_dyanmic) is presented in this paper. Experimental results are achieved by measuring the current distribution between two parallel connected IGBTs (rated at 600V, 90A). These experimental results indicate an improvement in average current imbalance of 74% and 65% for the turn on and off periods, respectively.
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Applied Power Electronics Conference and Exposition (APEC), 2013 Twenty-Eighth Annual IEEE
  • Conference_Location
    Long Beach, CA, USA
  • ISSN
    1048-2334
  • Print_ISBN
    978-1-4673-4354-1
  • Electronic_ISBN
    1048-2334
  • Type

    conf

  • DOI
    10.1109/APEC.2013.6520216
  • Filename
    6520216