Near-zero gate bouncing in high-frequency converters with shield-plate FETs

The gate bouncing of the Shield-Plate FETs (SP-FETs) in synchronous buck converters is investigated in this work for the first time. A comparative analysis between a 30V SP-FET and a 30V TP-FET (Trench Power MOSFET) working as a synchronous switch is provided by experimental results and mixed-mode simulation. Although the current conduction during the deadtime is due to different mechanisms, the extremely low Crss/Ciss ratio (< 0.01) is identified as the main responsible for the negligible gate bouncing in SP-FETs. The gate bouncing immunity is presented as a new paradigm for the circuit/device co-design, thus allowing the reduction of the driver deadtime and the MOSFET threshold voltage in order to achieve efficiency peaks above 90% for 12V-to-1.2V conversion at 1MHz operation frequency.