Stable high dV/dt switching of SiC JFETs using simple drive methods

Due to low on-resistance and low intrinsic capacitance the SiC JFET is capable of very high dV/dt in principle. However, these advantages often result in the excitation of resonant modes during switching. The low on on-resistance of the device results in less contributes little damping of to the L-C resonance in the circuit. Under conditions which are realizable in applications, the devices will manifest sustained oscillations. Typically these problems are addressed by reducing the switching speeds using various dissipative methods. These methods focus on symptomatic effects rather than causes. Careful consideration to parasitic inductances in circuit layout can yield very high dV/dt switching (e.g. < 30 V/ns) with only the need for modest series gate resistance to achieve stable operation. This paper demonstrates this effect experimentally, reporting the highest known switching rates of inductive currents for these devices to date.