DocumentCode
602633
Title
High-speed formal verification of heterogeneous coherence hierarchies
Author
Beu, J.G. ; Poovey, J.A. ; Hein, E.R. ; Conte, T.M.
Author_Institution
Georgia Inst. of Technol., Atlanta, GA, USA
fYear
2013
fDate
23-27 Feb. 2013
Firstpage
566
Lastpage
577
Abstract
As more heterogeneous architecture solutions continue to emerge, coherence solutions tailored for these architectures will become mandatory. Coherence hierarchies will likely continue to be prevalent in future large-scale shared memory architectures. However, past experience has shown that hierarchical coherence protocol design is a non-trivial problem, especially when considering the verification effort required to guarantee correctness. While some strategies do exist for verification of homogenous coherence hierarchies, support for reasonable verification of heterogeneous coherence hierarchies is currently unavailable. Ideally, hierarchical coherence protocols composed of `building block´ protocols should be able to take advantage of incremental verification to side step the state-space explosion problem which hampers any large-scale verification effort. In this work, we prove this can be accomplished through the use of the Manager-Client Pairing (MCP) framework, which provides encapsulation and permission checking support that enables a form of state-space symmetry. When combined with an inductive proof, this ensures the validation properties of proper permission distribution and livelock/deadlock freedom are enforced by any hierarchical composition of MCP compliant protocols. Demonstration of this methodology through the MurPhi formal verifier shows several orders of magnitude improvement in verification cost compared to full hierarchy verification.
Keywords
coherence; formal verification; protocols; shared memory systems; state-space methods; MCP compliant protocols; MCP framework; MurPhi formal verifier; deadlock; heterogeneous architecture solutions; heterogeneous coherence hierarchies; hierarchical coherence protocol design; high-speed formal verification; homogenous coherence hierarchies; incremental verification; large-scale shared memory architectures; large-scale verification effort; livelock; manager-client pairing framework; state-space explosion problem; state-space symmetry; validation properties; verification effort; Coherence; Computer architecture; Encapsulation; Explosions; Fractals; Protocols; Space exploration;
fLanguage
English
Publisher
ieee
Conference_Titel
High Performance Computer Architecture (HPCA2013), 2013 IEEE 19th International Symposium on
Conference_Location
Shenzhen
ISSN
1530-0897
Print_ISBN
978-1-4673-5585-8
Type
conf
DOI
10.1109/HPCA.2013.6522350
Filename
6522350
Link To Document