The first 22nm IA multi-CPU and GPU system-on-chip using tri-gate transistors

Author

Siers, Scott ; Damaraju, Satish ; George, V. ; Jahagirdar, Sanjeev ; Khondker, Tanveer ; Milstrey, Robert ; Sarkar, Santonu ; Stolero, Israel ; Subbiah, Arun

Author_Institution

Intel Corp., Folsom, CA, USA

fYear

2012

fDate

12-14 Nov. 2012

Firstpage

9

Lastpage

12

Abstract

This paper will go over some of the details of Intel´s latest Core offering, the first 22nm design code-named Ivy Bridge. In addition to the new process, Ivy Bridge offers several new features including significant improvements to the Graphics and Media block including DX11 support, new power/thermal control optimizations, support for 3 simultaneous displays, new security features and new PCIE Gen3 support. The new 22nm process provides exceptional low voltage performance advantage as well as a 2x improvement in density. The paper also reviews changes to leverage the low operating voltages as well as details of IO, PLL and clocking. Ivy Bridge was introduced into the market on April 23, 2012.

Keywords

circuit optimisation; graphics processing units; integrated circuit design; system-on-chip; transistors; GPU system-on-chip; IA multiCPU system-on-chip; IO; Intel architecture cores; Ivy bridge design code; PCIE Gen3 support; PLL; clocking; media block; power-thermal control optimizations; security features; size 22 nm; trigate transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid State Circuits Conference (A-SSCC), 2012 IEEE Asian

Conference_Location

Kobe

Type

conf

DOI

10.1109/IPEC.2012.6522610

Filename

6522610