Title :
A high performance 64Gb MLC NAND flash memory in 20nm CMOS technology
Author :
Jin-Su Park ; Byoung-Sung You ; Sang-Don Lee ; Kwangho Baek ; Chun-Woo Jeon ; Tai-kyu Kang ; Jae-Ho Lee ; Min-Su Kim ; Dae-il Choi ; Jae-Won Choi ; Hyun Jeong ; Jong-Woo Kim ; Eun-seong Jang ; Tae-Yun Kim ; Chang-Hyuk Lee ; Jong-Gi Nam ; Bong-Seok Han ; K
Author_Institution :
Flash Design Team III, SK Hynix Semicond. Inc., Icheon, South Korea
Abstract :
A 64Gb MLC NAND flash memory on 20nm CMOS technology has been developed. 135mm2 chip size is realized by 1-sided All-Bit-Line architecture and 128 cells in a string. 25MB/s program throughput with 2-bit/cell is achieved by reducing BL resistance and pump output loading using new BL control method and multi-split block decoder. This device also supports 400MB/s high speed interface.
Keywords :
CMOS memory circuits; NAND circuits; block codes; decoding; flash memories; 1-sided all-bit-line architecture; BL control method; BL resistance reduction; CMOS technology; bit rate 25 Mbit/s; bit rate 400 Mbit/s; high performance MLC NAND flash memory; high speed interface; multisplit block decoder; pump output loading; size 20 nm; storage capacity 64 Gbit;
Conference_Titel :
Solid State Circuits Conference (A-SSCC), 2012 IEEE Asian
Conference_Location :
Kobe
DOI :
10.1109/IPEC.2012.6522612
