Heterogeneous micro/nano-electronics: Towards the maturity learning into the zero variability era

Nanoelectronics will have to face major challenges in the next decades in order to proceed with increasing progress and drastically reduced to zero variability at the sub 10 nm nodes level. New progress laws combined to the scaling down of CMOS based technology will emerge to enable new paths to Functional Diversification. New materials and disruptive architectures, mixing logic and memories, Heterogeneous Integration, introducing 3D schemes at the Front End and Back End levels, will come into play to make it possible.