Advanced gate stack work function optimization and substrate dependent strain interactions on HKMG first stacks for 28nm VLSI ultra low power technologies

Author

Hoentschel, J. ; Shiang Yang Ong ; Balzer, T. ; Sassiat, N. ; Ran Yan ; Herrmann, Thomas ; Flachowsky, S. ; Grass, C. ; Beyer, Stefan ; Kallensee, O. ; Yu-Yin Lin ; Shickova, A. ; Muehlhoff, A. ; Kretzschmar, C. ; Winkler, J. ; Wiatr, M. ; Horstmann, M.

Author_Institution

GLOBALFOUNDRIES Dresden Module One Ltd. Liability Co. & Co. KG, Dresden, Germany

fYear

2013

fDate

19-21 March 2013

Firstpage

37

Lastpage

40

Abstract

Different gate stack optimizations and substrate dependent strain interactions have been studied and implemented in a cost-effective 28nm VLSI ultra low power technology. Drive current improvements for NFET I_D,SAT = 870μA/μm and PFET I_D,SAT = 465μA/μm at I_OFF = 1nA/μm and V_DS = 1V can be demonstrated by using compressive and tensile contact layers on (100)/<;110> substrates. Work function optimizations result in a proper threshold voltage adjustment and improved reliability behavior for 28nm ultra low power technologies. SOC level test design implementations show consistent yield as well as improved performance.

Keywords

VLSI; field effect transistors; integrated circuit design; integrated circuit reliability; low-power electronics; HKMG first stacks; NFET; SOC level test design implementations; advanced gate stack work function optimization; compressive contact layers; cost-effective VLSI ultra low power technology; reliability improvement; size 28 nm; substrate dependent strain interactions; tensile contact layers; threshold voltage adjustment; Logic gates; MOS devices; Reliability; Silicon; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Ultimate Integration on Silicon (ULIS), 2013 14th International Conference on

Conference_Location

Coventry

Print_ISBN

978-1-4673-4800-3

Electronic_ISBN

978-1-4673-4801-0

Type

conf

DOI

10.1109/ULIS.2013.6523485

Filename

6523485