Integration aspects of strained Ge pFETs

Author

Witters, L. ; Eneman, Geert ; Mitard, J. ; Vincent, B. ; Loo, Roger ; Hikavyy, Andriy ; Milenin, A.P. ; Mertens, Sofie ; Thean, A. ; Collaert, Nadine

Author_Institution

IMEC, Leuven, Belgium

fYear

2013

fDate

19-21 March 2013

Firstpage

49

Lastpage

52

Abstract

Strained Ge channel PFETs have the potential to outperform state-of-the-art strained Si channel PFETs. This paper describes the integration aspects for strained Ge channel devices based on TCAD simulations and experimental observations. Channel stress can be implemented by use of Si_1-xGe_x strain relaxed buffers (SRB) and/or high Ge- and Sn-content source/drain stressors. Thermal budget, damage and Ge loss have to be limited during process integration to maintain the high stress in the Ge channel till the end of the processing.

Keywords

Ge-Si alloys; elemental semiconductors; field effect transistors; germanium; technology CAD (electronics); tin; Ge; PFET; SRB; Si_1-xGe_x; Sn; TCAD simulations; channel stress; drain stressors; integration aspects; source stressors; strain relaxed buffers; strained channel devices; Logic gates; Silicon; Silicon germanium; Transistors; Germanium; strain; strain relaxed buffer;

fLanguage

English

Publisher

ieee

Conference_Titel

Ultimate Integration on Silicon (ULIS), 2013 14th International Conference on

Conference_Location

Coventry

Print_ISBN

978-1-4673-4800-3

Electronic_ISBN

978-1-4673-4801-0

Type

conf

DOI

10.1109/ULIS.2013.6523488

Filename

6523488