Modelling of reliability of nanoscale MOSFETs within the discrete charge trapping paradigm

Author

Adamu-Lema, F. ; Amoroso, Salvatore Maria ; Gerrer, Louis ; Asenov, Asen

Author_Institution

Univ. of Glasgow, Glasgow, UK

fYear

2013

fDate

19-21 March 2013

Firstpage

153

Lastpage

156

Abstract

A computational simulation study of oxide reliability degradation considering bias temperature instabilities and random telegraph noise in nano-scale transistors is presented. The interplay between statistical variability, induced by random dopant fluctuations, and reliability is discussed in details, within the framework of a discrete charge trapping paradigm. The stochastic behaviour of the key reliability figures of merit is analyzed by means of both static and dynamic oxide degradation simulations.

Keywords

MOSFET; semiconductor device models; semiconductor device reliability; statistical analysis; stochastic processes; computational simulation study; discrete charge trapping paradigm; dynamic oxide degradation simulations; nanoscale MOSFET reliability modelling; nanoscale transistors; oxide reliability degradation; random dopant fluctuations; random telegraph noise; static oxide degradation simulations; statistical variability; stochastic behaviour; temperature instabilities; Analytical models; CMOS integrated circuits; Computational modeling; Logic gates; Reliability; Semiconductor device modeling; Stochastic processes; BTI; CMOS; Charge-trapping; RTN; TAT; degradation; device simulation; reliability; variability;

fLanguage

English

Publisher

ieee

Conference_Titel

Ultimate Integration on Silicon (ULIS), 2013 14th International Conference on

Conference_Location

Coventry

Print_ISBN

978-1-4673-4800-3

Electronic_ISBN

978-1-4673-4801-0

Type

conf

DOI

10.1109/ULIS.2013.6523506

Filename

6523506