Mobility extraction assessment in GAA Si NW JL FETs with cross-section down to 5 nm

In this paper, we report for the first time, assessment on mobility extraction in equilateral triangular gate-all-around Si nanowire junctionless (JL) nMOSFETs with cross-section down to 5 nm. This analysis was performed in accumulation regime, as a first step, addressing bias-dependency of various key MOSFET parameters (e.g. series resistance, channel width and gate-channel capacitance), non-uniform electron density due to corners and quantization. A significant bias-dependent series resistance variation in JL MOSFETs is reported above flat-band, leading to a significant mobility extraction accuracy drop of ~50%. All quasistationary device simulations were done on 100 nm long channel devices with 5-20 nm NW width, 2 nm SiO₂ gate oxide thickness and 1×10¹⁹ cm^-3 n-type channel doping using a constant mobility model (100 cm²/V·s).