Characterization of thulium silicate interfacial layer for high-k/metal gate MOSFETs

Author

Dentoni Litta, E. ; Hellstrom, Per-Erik ; Henkel, C. ; Ostling, Mikael

Author_Institution

Sch. of ICT, KTH R. Inst. of Technol., Kista, Sweden

fYear

2013

fDate

19-21 March 2013

Firstpage

121

Lastpage

124

Abstract

The possibility of integrating thulium silicate as IL (interfacial layer) in scaled high-k/metal gate stacks is explored. Electrical properties of the silicate IL are investigated in MOS capacitor structures for the silicate formation temperature range 500-900 °C. Results are compared to lanthanum silicate. A CMOS-compatible process flow for silicate formation is demonstrated, providing EOT of the IL as low as 0.1-0.3 nm and interface state density at flatband below 2·10¹¹ cm^-2eV^-1. The silicate IL is found to be compatible with both gate-last and gate-first process flows, with a maximum thermal budget of 1000 °C.

Keywords

CMOS integrated circuits; MOSFET; lanthanum compounds; silicon compounds; thulium compounds; CMOS-compatible process flow; EOT; LaSiO; MOS capacitor structure; TmSiO; electrical property; for high-k/metal gate MOSFETs; gate-first process flow; gate-last process flow; scaled high-k/metal gate stack; silicate formation; temperature 500 C to 900 C; thulium silicate interfacial layer; Annealing; CMOS integrated circuits; Current measurement; Logic gates; Silicon; Surface treatment; Thickness measurement; LaSiO; TmSiO; high-k; interfacial layer; silicate;

fLanguage

English

Publisher

ieee

Conference_Titel

Ultimate Integration on Silicon (ULIS), 2013 14th International Conference on

Conference_Location

Coventry

Print_ISBN

978-1-4673-4800-3

Electronic_ISBN

978-1-4673-4801-0

Type

conf

DOI

10.1109/ULIS.2013.6523528

Filename

6523528