Configurable redundant via-aware standard cell design considering multi-via mechanism

Well designed redundant via-aware standard cells (SCs) can increase the redundant via1 insertion rate in cell-based designs. However, with conventional methods, manual and visual-based check are required to locate pins and tune geometries in layouts, which can be very time consuming and unreliable. Instead, an O(NlogN) via-aware standard cell optimization algorithm is developed. The proposed method considers various redundant via configurations such as double-via and rectangle-via which effectively increase the redundant via insertion rate for both concurrent routing and post-layout optimization. As a result, the proposed scheme not only addresses the problem of a low via1 insertion rate in nanometer regimes, but also demonstrates an efficient automatic layout optimizer for designing standard cells. Compared to the conventional standard library, the proposed method saves considerable design effort and time. Experimental results reveal that the proposed method effectively improves the redundant via1 insertion rate by a total of 26.3%.