Title :
System-level modelling of dynamic reconfigurable designs using functional programming abstractions
Author :
Uchevler, B.N. ; Svarstad, K. ; Kuper, Jan ; Baaij, C.
Author_Institution :
Dept. of Electron. & Telecommun., NTNU, Trondheim, Norway
Abstract :
With the increasing size and complexity of designs in electronics, new approaches are required for the description and verification of digital circuits, specifically at the system level. Functional HDLs can appear as an advantageous choice for formal verification and high-level descriptions. In this paper we explain how to use high-level structures and concepts like higher-order functions, and parametrization together with partial evaluation implementation technique, to describe run-time reconfigurable systems in Haskell. We use the CLaSH tool to translate high-level Haskell descriptions into RT level, synthesizable VHDL. A simple design is used to show the ideas and is implemented on Suzaku-sz410 board for practical proof of concept.
Keywords :
field programmable gate arrays; hardware description languages; logic design; CLaSH tool; FPGA design; RT level; Suzaku-sz410 board; digital circuit verification; dynamic reconfigurable designs; formal verification; functional HDL; functional programming abstractions; high-level Haskell descriptions; high-level descriptions; high-level structures; higher-order functions; partial evaluation implementation technique; run-time reconfigurable systems; synthesizable VHDL; system-level modelling; Consumer electronics; Digital signal processing; Field programmable gate arrays; Finite impulse response filters; Hardware; Software; Unified modeling language; Functional HDL; Partial Evaluation; Run-Time Reconfiguration; Self-Reconfiguration;
Conference_Titel :
Quality Electronic Design (ISQED), 2013 14th International Symposium on
Conference_Location :
Santa Clara, CA
Print_ISBN :
978-1-4673-4951-2
DOI :
10.1109/ISQED.2013.6523639
