Cost-efficient scheduling in high-level synthesis for Soft-Error Vulnerability Mitigation

Due to the continuous reduction in chip feature size and supply voltage, soft errors are becoming a serious problem in the today´s LSI design. Most literature on system-level design techniques has been conventionally tackling this issue by spatial and/or temporal modular redundancy, whose cost in circuit area and performance is large. This paper proposes a soft error-aware scheduling method in high-level synthesis (HLS), which does not rely on such expensive, conventional techniques. The reliability of the datapath circuit is determined not only by that of hardware resources to which operations and values are assigned, but also that of their active time (i.e., time during which operational results should be correct). By considering both of these factors, our proposed method schedules operations so that the reliability of HLS-generated datapath circuits can be maximized under designer-given area/latency constraints. Experimental results demonstrate the effectiveness of our method over existing methods, especially for strict area/latency constraints.