Design and Analysis of High Performance Voltage Controlled Ring Oscillator Using Replica Bias Circuit

In present paper, extremely robust design of Ring oscillator using various circuitry and differential stages of cmos inverter have been presented. In this design improvement in power consumption and several other parameters viz. slew rate, Tran conductance, leakage power and leakage current has been achieved by varying the input voltage. This paper describes power consumption variation of [2.811 to1.283] mW by varying input voltage from [1.8 to1.0] V at 180nm technology and improved power consumption of [190.12 to 48.40] ÂμW by varying input voltage from [1.7 to 0.7] V at 45nm technology with the generation of rapid frequency of 2.4 GHz. In this context, we have simulated a high speed ring oscillator using cascaded differential five stage delay cells by applying DC inversion, a biasing circuit and a tuning circuit using the cadence virtuoso tool, which is exceedingly applicable in ultra high speed Wi-Fi communications.