A Design Approach of Low Power VLSI for Downsampler Using Multirate Technique

Paper Presents Design Approach of Low Power VLSI using Multirate digital signal processing system which includes sampling rate conversion. This technique is necessary for systems with different input and output sampling rates, as the proposed multirate device is down sampler, FPGA implementation of the same is presented. The FPGA synthesis results are verified and report is presented. In order to build down sampler consisting of D F/F and clock generator, are downloaded on cyclone-II FPGA of ALTERA QUARTUS-II platform. The circuit obtained is verified and implemented successfully. Then it is synthesized using 45 nm library in synopsis tool with constraint of low power and area. Reduction of power consumption is important for VLSI system and also it becomes one of the most critical design parameter.