A Graph-Based Approach to Designing Parallel Multipliers over Galois Fields Based on Normal Basis Representations

This paper presents a graph-based approach to designing arithmetic circuits over Galois fields (GFs) using normal basis representations. The proposed method is based on a graph-based circuit description called Galois-field Arithmetic Circuit Graph (GF-ACG). First, we extend GF-ACG to describe GFs represented by normal basis in addition to polynomial basis. We then apply the extended design method to Massey-Omura parallel multipliers which are well known as typical multipliers based on normal basis. We present the formal description in a hierarchical manner and show that the verification time is greatly reduced as compared with that of the conventional simulation technique. In addition, we design GF exponentiation circuits consisting of the Massey-Omura parallel multipliers and evaluate the performance in comparison with that of polynomial-basis multipliers.