Title :
A Graph-Based Approach to Designing Parallel Multipliers over Galois Fields Based on Normal Basis Representations
Author :
Okamoto, K. ; Homma, Noriyasu ; Aoki, Toyohiro
Author_Institution :
Grad. Sch. of Inf. Sci., Tohoku Univ., Sendai, Japan
Abstract :
This paper presents a graph-based approach to designing arithmetic circuits over Galois fields (GFs) using normal basis representations. The proposed method is based on a graph-based circuit description called Galois-field Arithmetic Circuit Graph (GF-ACG). First, we extend GF-ACG to describe GFs represented by normal basis in addition to polynomial basis. We then apply the extended design method to Massey-Omura parallel multipliers which are well known as typical multipliers based on normal basis. We present the formal description in a hierarchical manner and show that the verification time is greatly reduced as compared with that of the conventional simulation technique. In addition, we design GF exponentiation circuits consisting of the Massey-Omura parallel multipliers and evaluate the performance in comparison with that of polynomial-basis multipliers.
Keywords :
Galois fields; circuit simulation; graph theory; logic design; multiplying circuits; polynomials; GF exponentiation circuit design; GF-ACG; Galois-field arithmetic circuit graph design; Massey-Omura parallel multiplier design; graph-based circuit description approach; normal basis representation; polynomial; Adders; Algorithm design and analysis; Hardware design languages; Integrated circuit modeling; Niobium; Polynomials; arithmetic circuits; computer algebra; formal verification; normal basis;
Conference_Titel :
Multiple-Valued Logic (ISMVL), 2013 IEEE 43rd International Symposium on
Conference_Location :
Toyama
Print_ISBN :
978-1-4673-6067-8
Electronic_ISBN :
0195-623X
DOI :
10.1109/ISMVL.2013.5