Title :
Comparing Performance of a Multiple-Valued Time-Based Serial Data Link with Other Serial Links
Author :
Rashdan, M. ; Haslett, J.W.
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Calgary, Calgary, AB, Canada
Abstract :
A comparison between the multiple-valued differential-time-signaling (MVDTS) link and other serial links is presented in this paper. An example of a 4-bit 1.6Gbps serial link has been designed and simulated using SerDes and differential-time-signaling (DTS) architectures. A commercial FPGA kit has been used to implement the simulated serial links and the results have been compared to the simulated results. In addition, a 6-bit 15Gbps serial link has been designed using SerDes, DTS and MVDTS links. A comparison among the three links, based on the simulated results in terms of design details and spectral content, is provided. The MVDTS shows advantages over the two other serial links, in that it concentrates the transmitted signal energy in lower bandwidth compared to the DTS and SerDes links, uses much lower input clock frequency compared to the SerDes link for the same link rate, and has better jitter characteristics.
Keywords :
field programmable gate arrays; jitter; logic design; MVDTS link; SerDes links; bit rate 1.6 Gbit/s; bit rate 15 Gbit/s; commercial FPGA kit; design details; differential-time-signaling architecture; jitter characteristics; lower input clock frequency; multiple-valued differential-time-signaling link; multiple-valued time-based serial data link; spectral content; Bandwidth; Circuit synthesis; Clocks; Discrete Fourier transforms; Receivers; Signal resolution; Transmitters; PPM; SerDes; TDC; multiple-valued DTS;
Conference_Titel :
Multiple-Valued Logic (ISMVL), 2013 IEEE 43rd International Symposium on
Conference_Location :
Toyama
Print_ISBN :
978-1-4673-6067-8
Electronic_ISBN :
0195-623X
DOI :
10.1109/ISMVL.2013.19
