Debugging of Reversible Circuits Using pDDs

Different kinds of decision diagrams have played key roles in advancements for the synthesis of reversible circuits in the recent past. In this work, decision diagrams are used to efficiently debug reversible circuits in cases when they do not match their intentional specification. It can automatically be checked whether the faulty circuit is almost equal to a given function, i.e. it can realize the function by slightly modifying the circuit, e.g. by adding or changing a gate. For this purpose, πDDs are used which allow for a compact representation of a set of permutations.