A 10-T SRAM cell with inbuilt charge sharing for dynamic power reduction

In this paper we present a novel 10T SRAM cell design with an inbuilt mechanism for charge recycling to cut down the dynamic power budget. The read discharge power of a single ended 8T cell is reused efficiently in the proposed cell architecture. The fundamental premise of our approach is that the read current in an 8T SRAM cell can be recycled in the write bitlines to reduce the read bitline and write bitline swings simultaneously. The proposed 10T SRAM cell limits the read bitline swing and reduces the read power consumption by 67%. The write `0´ and write `1´ powers are also reduced by 23.12% and 30.65% respectively. The impact of the proposed cell on the delay has also been analyzed. Bitline leakage is also reduced by 65%. These improvements in the results of the proposed cell validate our approach. The design is simulated at 90 nm technology and frequency of 333 MHz.