Analysis of gate engineered SOI MOSFET for VLSI application

Author

Ramya, M.S.A. ; Nirmal, D. ; Soman, Sumit ; Nair, P.P. ; Jeba, I.K.

Author_Institution

Dept. of Electron. & Commun. Eng., Karunya Univ., Coimbatore, India

fYear

2013

fDate

22-23 March 2013

Firstpage

498

Lastpage

501

Abstract

The Dual (DM) Trigate Silicon On Insulator (SOI) Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is designed and simulated using Sentaurus TCAD tools and its various parameters are analyzed. The Dual Material Trigate MOSFET has better ON current and reduced leakage current which results in better performance of the device. The ON current obtained is 2.301×10^-5 A/μm, the leakage current is 1.793×10^-12 A/μm and the perfect ON/OFF ratio is obtained. The technology used here is 22nm.

Keywords

MOSFET; VLSI; circuit simulation; integrated circuit design; integrated circuit modelling; leakage currents; silicon-on-insulator; technology CAD (electronics); DM; ON current; ON-OFF ratio; Sentaurus TCAD tool; VLSI application; dual trigate silicon on insulator; gate engineered SOI MOSFET analysis; leakage current reduction; metal oxide semiconductor field effect transistor; size 22 nm; Leakage currents; Logic gates; MOSFET; Performance evaluation; Substrates; Threshold voltage; Dual Material gate (DMG); Tri-gate (TG); drain induced barrier lowering (DIBL); short channel effect (SCE); silicon on insulater (SOI);

fLanguage

English

Publisher

ieee

Conference_Titel

Automation, Computing, Communication, Control and Compressed Sensing (iMac4s), 2013 International Multi-Conference on

Conference_Location

Kottayam

Print_ISBN

978-1-4673-5089-1

Type

conf

DOI

10.1109/iMac4s.2013.6526464

Filename

6526464