Design of peak detector and sub-flash architecture for adaptive resolution of flash ADC

Here we have proposed a design of Peak Detector and Sub-Flash architecture for adaptive Resolution ADC in 90nm Technology. The control circuits are developed for Adaptive Resolution for Flash ADC. Peak detector circuits will consist of peak detector for variable resolution and sub-flash architecture for reconfigurability. The voltages from the Bias block are used to provide a control voltage for Peak Detector circuits. The Transient analysis for peak detector circuits are tested for pulse and sinusoidal input voltage and the settling time is reported to be 5ns and 10ns. For reconfigurability, the input voltage vin is compared with Bias Block voltages for achieving the resolution i.e, 4-, 5-, 6-bit respectively. Sub flash block consist of comparators, Mux and Decoder circuit. Rail to rail comparators are used for decision making of resolution selectivity. Process corner analysis is carried out for comparators to check process variation dependency of analog circuit. This reconfigurable architecture is clubbed with Threshold Inverter quantized (TIQ) ADC to get 4-, 5-, and 6-bit resolution depending upon input applied which provides large amount of power saving.