DocumentCode :
604704
Title :
Design of peak detector and sub-flash architecture for adaptive resolution of flash ADC
Author :
Palsodkar, Prasanna ; Dakhole, P. ; Palsodkar, Prasanna ; Chandekar, O.
Author_Institution :
Dept. of Electron. Eng., YCCE, Nagpur, India
fYear :
2013
fDate :
22-23 March 2013
Firstpage :
780
Lastpage :
784
Abstract :
Here we have proposed a design of Peak Detector and Sub-Flash architecture for adaptive Resolution ADC in 90nm Technology. The control circuits are developed for Adaptive Resolution for Flash ADC. Peak detector circuits will consist of peak detector for variable resolution and sub-flash architecture for reconfigurability. The voltages from the Bias block are used to provide a control voltage for Peak Detector circuits. The Transient analysis for peak detector circuits are tested for pulse and sinusoidal input voltage and the settling time is reported to be 5ns and 10ns. For reconfigurability, the input voltage vin is compared with Bias Block voltages for achieving the resolution i.e, 4-, 5-, 6-bit respectively. Sub flash block consist of comparators, Mux and Decoder circuit. Rail to rail comparators are used for decision making of resolution selectivity. Process corner analysis is carried out for comparators to check process variation dependency of analog circuit. This reconfigurable architecture is clubbed with Threshold Inverter quantized (TIQ) ADC to get 4-, 5-, and 6-bit resolution depending upon input applied which provides large amount of power saving.
Keywords :
analogue integrated circuits; analogue-digital conversion; comparators (circuits); invertors; transient analysis; voltage control; Mux circuit; TIQ ADC; adaptive resolution ADC; analog circuit; bias block voltages; comparators; control circuits; decision making; decoder circuit; flash ADC; peak detector circuits; reconfigurability; size 90 nm; subflash architecture; threshold inverter quantized ADC; time 10 ns; time 5 ns; transient analysis; voltage control; CMOS integrated circuits; Decoding; Detectors; Gain; MOSFET circuits; Rails; Signal resolution; Adaptivity; Peak Detector; Reconfigurable; Variable Resolution;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Automation, Computing, Communication, Control and Compressed Sensing (iMac4s), 2013 International Multi-Conference on
Conference_Location :
Kottayam
Print_ISBN :
978-1-4673-5089-1
Type :
conf
DOI :
10.1109/iMac4s.2013.6526512
Filename :
6526512
Link To Document :
بازگشت