Novel transistor level realization of ultra low power high-speed adiabatic Vedic multiplier

In this paper, we describe an energy-efficient Vedic multiplier structure using Energy Efficient Adiabatic Logic (EEAL). The power consumption of the proposed multiplier is significantly low because the energy transferred to the load capacitance is mostly recovered. The proposed 8×8 CMOS and adiabatic multiplier structure have been designed in a TSMC 0.18 μm CMOS process technology and verified by Cadence Design Suite. Both simulation and measurement results verify the functionality of such logic, making it suitable for implementing energy-aware and performance-efficient very-large scale integration (VLSI) circuitry.