Design and Analysis of a Robust, High Speed, Energy Efficient 18 Transistor 1-bit Full Adder Cell, Modified with the Concept of MVT Scheme

Optimization of power and speed is the most crucial issue for any low-voltage, low-power design. In this paper an Energy Efficient, Robust 18 Transistor (18T) 1-bit Full Adder (FA) cell, modified with the concept of Mixed Threshold Voltage (MVT) scheme, is reported. The entire design is done in 45nm technology, and compared to the conventional one, a considerable amount of reduction in the Average Power consumption (P_avg) as well as the Power Delay Product (PDP) has been achieved. For an operating frequency of 500MHz, the Pavg is as low as 9.31×10-8 Watt, whereas the PDP for Sum output is found to be 1.115×10-18 Joule. The analyses have been carried out with help of the simulation runs on SPICE, and that indicate, for the lower Supply Voltages (V_dd), MVT scheme can be a more practical option than the simple dual threshold technique.