CSP-Filling: A New X-Filling Technique to Reduce Capture and Shift Power in Test Applications

In this paper, we present a new X-filling technique to reduce the shift and capture transitions occurred during scan based test application. The unspecified bits in the test cubes are filled with the logic value of 1´s or 0´s using the proposed don´t care filling technique, namely CSP - filling in such a way that the both average power and peak power in test applications are reduced. In our approach, the capture transition is made to be within the peak-power limit of the circuit under test while reducing the average power in shift-in phase of test applications. The experimental results obtained from ISCAS´89 benchmark circuits show that, the CSP - filling technique provides a significant reduction in both shift and capture transitions in test mode.