DocumentCode
604738
Title
From Requirements and Scenarios to ESL Design in SystemC
Author
Le, Hoang M. ; Grosse, Daniel ; Drechsler, Rolf
Author_Institution
Inst. of Comput. Sci., Univ. of Bremen, Bremen, Germany
fYear
2012
fDate
19-22 Dec. 2012
Firstpage
183
Lastpage
187
Abstract
In the ESL design flow, the crucial task of developing a golden model that correctly implements the natural-language top-level specification has received little attention so far. The major drawback of the current practice is the isolation of design and verification. Motivated by this and the recent advance of verification techniques for SystemC ESL models, we propose a novel methodology to develop a correct SystemC golden model from the top-level specification. The proposed methodology is driven by the requirements and the scenarios in the specification with design and verification going hand in hand. An early formalization of requirements and scenarios produces a set of properties and a testbench together with a code skeleton that will be successively extended to a full SystemC ESL model. The availability of properties and a testbench beforehand enables verification-driven development of the model. The advantages of the methodology are discussed and demonstrated by a case study.
Keywords
formal specification; formal verification; hardware description languages; system-on-chip; ESL design flow; SystemC golden model; code skeleton; full SystemC ESL model; natural-language top-level specification; requirement formalization; scenario formalization; verification technique; verification-driven development; SystemC; formal methods; system-level design methodology;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronic System Design (ISED), 2012 International Symposium on
Conference_Location
Kolkata
Print_ISBN
978-1-4673-4704-4
Type
conf
DOI
10.1109/ISED.2012.36
Filename
6526580
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