The Impact of Process-Induced Mechanical Stress in Narrow Width Devices and Circuit Design Issues

In this work we present a simulation based study of the impact of process-induced mechanical stress in narrow width devices and its implication on circuit design. We observe that the channel stress and hence drive current of narrow width devices significantly depend upon the actual width of a device. We present a model for estimating width dependent channel stress and effective drive current in strain engineered devices. Width dependent change in drive strength causes W_P/W_N ratio (also referred to as ´ß´) in inverters to change with inverter scaling factor ´S´. If not accounted for, this results into a suboptimal circuit design. Finally with the help of CMOS tapered buffer design examples we show that assigning ß individually to each stage while considering the narrow width effects (NWE) results into simultaneous improvement in delay, power and silicon area.