Comparative analysis for hardware circuit architecture of Wallace tree multiplier

Multiplication is fundamental and significant operation of Electronic Circuits. Low power multipliers with high clock frequencies are widely used in today´s digital signal processing. Currently demand is power efficient, high speed miniature system which leads to design circuits with transistor level optimization. Full adder circuit is basic block of multiplier. Transistor level optimization of basic building element directly results in reduction of delay and power. In this paper, the performance analysis of Wallace-tree multiplier architectures are carried out based on small size full adder circuits.