Robust polysilicon gate FinFET SRAM design using dynamic back-gate bias

In this paper, polysilicon gate FinFET SRAM back-gate design is investigated. First, a previous approach for increasing the read stability is revisited and a device approach is proposed to alleviate the increased access time. Second, a dynamic back-gate design for pull up transistors is presented. In this design, the proposed circuitry can be shared for each row or column, so its area penalty is negligible.