DocumentCode :
605548
Title :
Efficient technique for Si validation of level shifters
Author :
Sharma, Parmanand ; Smith, Brian ; Hall, David ; Nelson, Mark ; Lohani, U.
Author_Institution :
Freescale Semicond., Noida, India
fYear :
2013
fDate :
25-28 March 2013
Firstpage :
207
Lastpage :
211
Abstract :
This paper presents a new structure that uses an addressable parametric array to validate level shifter cells. This structure is very area efficient and allows direct measurement of input and output voltages. Being a parametric structure enabled direct measurement of the output voltages, a critical parameter for level shifters. Experimental data confirmed the utility of this approach, validating level shifters in three different power domains including source biasing on the same 22-pad design. The simulation results show good correlation with the measured data.
Keywords :
buffer circuits; elemental semiconductors; logic arrays; silicon; voltage measurement; 22-pad design; Si; addressable parametric array; buffer cell; level shifter cell; source biasing; validation; voltage measurement; Arrays; Current measurement; Probes; Semiconductor device measurement; Standards; Switches; Voltage measurement; Level shifters; Si validation; addressable array;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Microelectronic Test Structures (ICMTS), 2013 IEEE International Conference on
Conference_Location :
Osaka, Japan
ISSN :
1071-9032
Print_ISBN :
978-1-4673-4845-4
Electronic_ISBN :
1071-9032
Type :
conf
DOI :
10.1109/ICMTS.2013.6528173
Filename :
6528173
Link To Document :
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