Title :
Mosaic SRAM Cell TEGs with intentionally-added device variability for confirming the ratio-less SRAM operation
Author :
Okamura, Hiroyuki ; Saito, Takashi ; Goto, Hiromi ; Yamamoto, Manabu ; Nakamura, Kentaro
Author_Institution :
Center for Microelectron. Syst., Kyushu Inst. of Technol., Iizuka, Japan
Abstract :
MOSAIC SRAM Cell TEGs consisting of memory cells having all combinations of gate sizes of transistors differing by two orders of magnitude were developed with 0.18 μm CMOS process to verify the operation margins for SRAM circuits. The measured results show the operation of the ratio-less SRAM is completely independent of the size of transistors in the memory cell.
Keywords :
CMOS memory circuits; SRAM chips; CMOS process; Mosaic SRAM cell TEG; SRAM circuits; gate size; intentionally-added device variability; memory cells; operation margins; ratioless SRAM operation; size 0.18 mum; transistor gate size; Arrays; Layout; Logic gates; SRAM cells; Transistors; Wireless sensor networks; Ratio-less; SRAM; Static Noise Margin; Variability;
Conference_Titel :
Microelectronic Test Structures (ICMTS), 2013 IEEE International Conference on
Conference_Location :
Osaka, Japan
Print_ISBN :
978-1-4673-4845-4
Electronic_ISBN :
1071-9032
DOI :
10.1109/ICMTS.2013.6528174
