High speed architecture for Variable Block Size Motion Estimation in H.264

By the arrival of latest video standards viz. MPEG-4 part 10 and H.264/H.26L, the usages of Advanced Video Coding (AVC) especially in the part of Variable Block Size (VBS) Motion Estimation (ME) are rising. A new architecture is developed for variable block size motion estimation using full search algorithm in this paper. There are two calculations carried out in this paper block size, which is variable, and another is the Sum of Absolute Differences (SAD), which are presented by recycling the outputs of reduced sub-block calculations. Mechanism that is incorporated by every processing element is shuffling mechanism. HDL verification is done through ModelSim simulator to verify the functionality. The design is implemented using TSMC 90nm CMOS technology. The frequency of the motion estimation block is 323.20 MHz, which can treat up to 41 Motion Vectors (MV).