• DocumentCode
    605865
  • Title

    Varying probability of droop fault depending on probabilistic nature of logic gates

  • Author

    Chakraborty, Nilanjan ; Acharya, Sanjeev

  • Author_Institution
    Dept. of Inf. Technol., Nat. Inst. of Technol., Durgapur, India
  • fYear
    2013
  • fDate
    25-26 March 2013
  • Firstpage
    472
  • Lastpage
    475
  • Abstract
    A fault in VLSI logic may encourage to happen another fault in the circuit and may the circuit causes malfunctioning. But if a fault discourage another fault to happen that would be an interesting area of our concern. In this paper we have focused on the droop fault and probabilistic logic gates fault in the VLSI circuit and observe that probabilistic nature of the logic gates might sometime stop a droop fault to occur, without affecting the desired output of the circuit.
  • Keywords
    VLSI; logic gates; VLSI logic; aggressor list; droop fault probability; probabilistic logic gates; Circuit faults; Error probability; Integrated circuit modeling; Integrated circuit reliability; Logic gates; Probabilistic logic; Very large scale integration; Aggressor list; Droop fault; Probabilistic logic gate; VLSI circuit; Via;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Emerging Trends in Computing, Communication and Nanotechnology (ICE-CCN), 2013 International Conference on
  • Conference_Location
    Tirunelveli
  • Print_ISBN
    978-1-4673-5037-2
  • Type

    conf

  • DOI
    10.1109/ICE-CCN.2013.6528545
  • Filename
    6528545