• DocumentCode
    606124
  • Title

    Impact of encroaching length and taper on double gate tunnel FET performance using TCAD simulations

  • Author

    Sugi, S.Shinly Swarna ; Nagarajan, K.K. ; Srinivasan, Rajagopalan

  • Author_Institution
    IT Department, SSN College of Engineering, Chennai, India
  • fYear
    2013
  • fDate
    20-21 March 2013
  • Firstpage
    942
  • Lastpage
    947
  • Abstract
    A double gate Tunnel FET structure with taper at the source-channel junction with source region encroaching further into the channel is studied using TCAD simulations. The device simulations have been implemented for different taper angles and source encroachment length, and the transfer characteristics (ID-VG) are studied. An optimum taper angle is seen for the device with a particular source encroachment length, considering the drive current (ION) as metric.
  • Keywords
    Insulators; Logic gates; MOSFET; Performance evaluation; Tunneling; Encroaching length; TCAD; Taper; Tunnel FET;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits, Power and Computing Technologies (ICCPCT), 2013 International Conference on
  • Conference_Location
    Nagercoil
  • Print_ISBN
    978-1-4673-4921-5
  • Type

    conf

  • DOI
    10.1109/ICCPCT.2013.6528880
  • Filename
    6528880
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=606124