Low latency VLSI architecture of S-box for AES encryption

This paper presents delay improved VLSI architecture of S-box for Advance Encryption Standard (AES) algorithm. The proposed architecture is implemented in FPGA. The delay, area and power comparison with some existing S-box architecture have been done. The comparison results show delay improvement along with low power consumption with constant area in terms of FPGA slices. The silicon validity is done by programming the XC2VP30 device of Xilinx FPGA with VHDL code for the proposed architecture. The architecture is also implemented in ASIC using 0.18 µm standard cell technology library which shows delay improvement of about 16 percent.