Skew and power reduction using tunable clock buffers and inverters

Clock signal plays a typical role in any synchronous IC design. The two important design parameters considered in clock design is clock skew and power, it has the highest switching activity and consumes major part of the total system power. As the technology shrinks, clock skew consumes larger part of clock period and also leakage power increases due to subthreshold leakage current. This paper presents the design of tunable clock buffers and inverters that can be used in backend of design process i.e., in clock tree synthesis (CTS). Layouts are drawn for designed tunable clock buffers and inverters. The results are obtained using cadence tool.