Efficient VLSI architecture of medium throughput AES encryption

This paper presents an efficient VLSI architecture design of Advanced Encryption Standard (AES) algorithm for medium throughput applications. The architecture stores the Round Key in ROM instead of registers. The proposed AES architecture for encryption has been implemented in XC2VP30 device on Xilinx Virtex-II FPGA board. With low hardware utilization, it achieves a medium throughput of 1.2 Gbps and also it has low power dissipation.