An optimized analog layout for a Low Power 3-bit flash type ADC modified with the CMOS inverter based comparator designs

This paper introduces a Low Power 3-bit flash type ADC (Analog-to-Digital Converter) where the conventional comparators have been replaced with the CMOS inverter based comparator designs. The reported structure of the ADC is designed using 180nm technology and it consumes 130.9 µWatt of average power while operating with an input frequency (fIN) of 30MHz, and a supply voltage of 1.8 Volt. Moreover, with the aim of increasing the design efficiency, an optimized analog layout, which occupies an area of 0.068mm², has been presented.