Design of high performance folded DIF FFT architecture using MMCM approach with Hcub algorithm

This paper propose the high performance FFT architecture by minimization of power using the Multiplier less Multiple Constant Multiplication (MMCM) approach. In the recent applications, hardware engineers have continuously tried to design a well-organized FFT architecture in an efficient manner. In the proposed architecture has the MCM system in which the multiplier can be replaced by using the adders/subtractors and the shifts operations. The addition and shift operations that realize the complex multiplication with the help of Heuristic Cumulative Benefit (Hcub) algorithm and it uses folding transformation which reduces the power consumption in the architecture. FFT architecture has a butterfly structure which act as a important part in the multiplications by constants, this can be reduced by using the MCM approach. Thus, the MCM with Hcub algorithm in the butterflies can effectively reduce the number of real as well as imaginary multiplications by constants. Thus the folded FFT hardware architectures with are widely used for low area and low power consumption overall which produce high performance architecture.