Efficient implementation of Convolution Encoder and Viterbi Decoder

This paper describes about the Convolution Encoder and Viterbi Decoder algorithm. The main aim is to achieve encoding and decoding rate as per WiMAX standard. Here, Convolution Encoder and Viterbi Decoder of code rate ½, constraint length 7; generator polynomial (171,133) has been implemented on EP4SGX70HF35C2 device of Stratix IV family in Altera DE board. Coding style of VHDL is used. The design has been synthesized using Altera Quartus II v11.0 and has been simulated using ModelSim Altera Starter Edition 6.6d. The comparison results show a large improvement in area.