Soft Error-Tolerant Design of MRAM-Based Nonvolatile Latches for Sequential Logics

Magnetoresistive memories, such as spin-transfer torque random access memory and magnetic latches (M-latch), are emerging memory technologies that offer attractive features, such as high density, low leakage, and nonvolatility as compared with conventional static memory. In this paper, we have proposed two single-event upset tolerant M-latch circuits in which their CMOS peripheral circuits are robust against radiation effects. Similar to the conventional M-latch circuit, our proposed M-latches employ two magnetic tunnel junction elements. Therefore, they consume almost the same energy consumption in comparison with nonprotected M-latch circuit. The simulation results of comparison with previous work show that our proposed radiation hardened M-latches consume less energy, occupy less area, and in case of a particle strike, offer lower restoring time. Furthermore, we have thoroughly investigated the robustness of our proposed radiation-hardened M-latches against single-event multiple effects and also in the presence of process variation as serious reliability challenges in emerging nanometer scale technologies.